In a digital communications system it is frequently necessary to accept data from a remote source and synchronize it to a local or output clock. One example of this is an incoming time division multiplex (TDM) data stream whose various data channels must be routed to separate destinations through a TDM switching center. A conventional way of handling this situation is to use a double rank register. The received data is shifted in serially by the received or input clock, a parallel transfer is made to the output register, and the data is sent out under the control of the local or output clock. This method is useful for transferring short bursts of data.
Where two asynchronous systems must be buffered for longer intervals, random access memories are used. The technique is to write the input data into the random access memory using the received clock to operate a sequential address counter. At some later time, the memory is read out by addressing it through a counter operated by the local or output clock. While the data is being read out, the new received data must be stored in a different memory chip because a memory cannot be written into and read from simultaneously. This method therefore requires a multiplicity of memory chips, and the arrangement overflows when both input and output address counters attempt to access the same memory chip. If the buffer is composed of n memory chips of k bits each, and is initialized to half full, the maximum buffering time can be defined as: EQU t = (1/2kn-k) /.DELTA.f
where .DELTA.f is the frequency difference between the input and output clocks. This arrangement thus has two shortcomings: It requires a plurality of memory chips, and it wastes k bits of memory. There is a need for an improved elastic buffer including a single read-write memory chip, and having a maximum buffering time defined as: EQU t = 1/2kn/.DELTA.f